# Reading C:/Dev/intelFPGA_lite/17.1/modelsim_ase/tcl/vsim/pref.tcl
# do load_sim.tcl
# obj/default/runtime/sim
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with novopt option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Platform Designer base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
#  ld
# [exec] dev_com
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:40 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/verbosity_pkg.sv -work altera_common_sv_packages 
# -- Compiling package verbosity_pkg
# 
# Top level modules:
# 	--none--
# End time: 13:45:40 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:40 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv -L altera_common_sv_packages -work error_adapter_0 
# -- Compiling module Nios2Computer_mm_interconnect_0_avalon_st_adapter_error_adapter_0
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_avalon_st_adapter_error_adapter_0
# End time: 13:45:40 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:40 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_avalon_st_adapter.v -work avalon_st_adapter 
# -- Compiling module Nios2Computer_mm_interconnect_0_avalon_st_adapter
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_avalon_st_adapter
# End time: 13:45:40 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:40 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_rsp_mux_001.sv -L altera_common_sv_packages -work rsp_mux_001 
# -- Compiling module Nios2Computer_mm_interconnect_0_rsp_mux_001
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_rsp_mux_001
# End time: 13:45:40 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:40 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_arbitrator.sv -L altera_common_sv_packages -work rsp_mux_001 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 13:45:40 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:40 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_rsp_mux.sv -L altera_common_sv_packages -work rsp_mux 
# -- Compiling module Nios2Computer_mm_interconnect_0_rsp_mux
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_rsp_mux
# End time: 13:45:40 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:40 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_arbitrator.sv -L altera_common_sv_packages -work rsp_mux 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 13:45:40 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:40 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_rsp_demux_002.sv -L altera_common_sv_packages -work rsp_demux_002 
# -- Compiling module Nios2Computer_mm_interconnect_0_rsp_demux_002
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_rsp_demux_002
# End time: 13:45:40 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:41 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_rsp_demux.sv -L altera_common_sv_packages -work rsp_demux 
# -- Compiling module Nios2Computer_mm_interconnect_0_rsp_demux
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_rsp_demux
# End time: 13:45:41 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:41 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_cmd_mux_002.sv -L altera_common_sv_packages -work cmd_mux_002 
# -- Compiling module Nios2Computer_mm_interconnect_0_cmd_mux_002
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_cmd_mux_002
# End time: 13:45:41 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:41 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_arbitrator.sv -L altera_common_sv_packages -work cmd_mux_002 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 13:45:41 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:41 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_cmd_mux.sv -L altera_common_sv_packages -work cmd_mux 
# -- Compiling module Nios2Computer_mm_interconnect_0_cmd_mux
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_cmd_mux
# End time: 13:45:41 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:41 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_arbitrator.sv -L altera_common_sv_packages -work cmd_mux 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 13:45:41 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:41 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_cmd_demux_001.sv -L altera_common_sv_packages -work cmd_demux_001 
# -- Compiling module Nios2Computer_mm_interconnect_0_cmd_demux_001
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_cmd_demux_001
# End time: 13:45:41 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:41 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_cmd_demux.sv -L altera_common_sv_packages -work cmd_demux 
# -- Compiling module Nios2Computer_mm_interconnect_0_cmd_demux
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_cmd_demux
# End time: 13:45:41 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:41 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv -L altera_common_sv_packages -work nios2_cpu_data_master_limiter 
# -- Compiling module altera_merlin_traffic_limiter
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(531): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(602): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(603): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(604): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(605): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(606): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(607): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(612): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(614): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(617): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(618): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(644): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(646): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(647): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(648): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(649): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(650): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(655): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(657): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(660): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_traffic_limiter.sv(661): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# 
# Top level modules:
# 	altera_merlin_traffic_limiter
# End time: 13:45:41 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 21
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:41 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_reorder_memory.sv -L altera_common_sv_packages -work nios2_cpu_data_master_limiter 
# -- Compiling module altera_merlin_reorder_memory
# -- Compiling module memory_pointer_controller
# 
# Top level modules:
# 	altera_merlin_reorder_memory
# End time: 13:45:41 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:42 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_avalon_sc_fifo.v -L altera_common_sv_packages -work nios2_cpu_data_master_limiter 
# -- Compiling module altera_avalon_sc_fifo
# 
# Top level modules:
# 	altera_avalon_sc_fifo
# End time: 13:45:42 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:42 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_avalon_st_pipeline_base.v -L altera_common_sv_packages -work nios2_cpu_data_master_limiter 
# -- Compiling module altera_avalon_st_pipeline_base
# 
# Top level modules:
# 	altera_avalon_st_pipeline_base
# End time: 13:45:42 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:42 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_router_004.sv -L altera_common_sv_packages -work router_004 
# -- Compiling module Nios2Computer_mm_interconnect_0_router_004_default_decode
# -- Compiling module Nios2Computer_mm_interconnect_0_router_004
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_router_004
# End time: 13:45:42 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:42 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_router_002.sv -L altera_common_sv_packages -work router_002 
# -- Compiling module Nios2Computer_mm_interconnect_0_router_002_default_decode
# -- Compiling module Nios2Computer_mm_interconnect_0_router_002
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_router_002
# End time: 13:45:42 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:42 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_router_001.sv -L altera_common_sv_packages -work router_001 
# -- Compiling module Nios2Computer_mm_interconnect_0_router_001_default_decode
# -- Compiling module Nios2Computer_mm_interconnect_0_router_001
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_router_001
# End time: 13:45:42 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:42 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0_router.sv -L altera_common_sv_packages -work router 
# -- Compiling module Nios2Computer_mm_interconnect_0_router_default_decode
# -- Compiling module Nios2Computer_mm_interconnect_0_router
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0_router
# End time: 13:45:42 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:42 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_avalon_sc_fifo.v -work jtag_uart_avalon_jtag_slave_agent_rsp_fifo 
# -- Compiling module altera_avalon_sc_fifo
# 
# Top level modules:
# 	altera_avalon_sc_fifo
# End time: 13:45:42 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:42 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_slave_agent.sv -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_agent 
# -- Compiling module altera_merlin_slave_agent
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_slave_agent.sv(618): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_slave_agent.sv(488): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_slave_agent.sv(489): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_slave_agent.sv(490): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_slave_agent.sv(491): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_slave_agent.sv(34): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.
# 
# Top level modules:
# 	altera_merlin_slave_agent
# End time: 13:45:42 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 6
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:42 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_agent 
# -- Compiling module altera_merlin_burst_uncompressor
# 
# Top level modules:
# 	altera_merlin_burst_uncompressor
# End time: 13:45:42 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:42 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_master_agent.sv -L altera_common_sv_packages -work nios2_cpu_data_master_agent 
# -- Compiling module altera_merlin_master_agent
# 
# Top level modules:
# 	altera_merlin_master_agent
# End time: 13:45:43 on Feb 18,2018, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:43 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_slave_translator.sv -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_translator 
# -- Compiling module altera_merlin_slave_translator
# 
# Top level modules:
# 	altera_merlin_slave_translator
# End time: 13:45:43 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:43 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_merlin_master_translator.sv -L altera_common_sv_packages -work nios2_cpu_data_master_translator 
# -- Compiling module altera_merlin_master_translator
# 
# Top level modules:
# 	altera_merlin_master_translator
# End time: 13:45:43 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:43 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu.vo -work cpu 
# -- Compiling module Nios2Computer_nios2_cpu_cpu
# 
# Top level modules:
# 	Nios2Computer_nios2_cpu_cpu
# End time: 13:45:43 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:43 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_debug_slave_sysclk.v -work cpu 
# -- Compiling module Nios2Computer_nios2_cpu_cpu_debug_slave_sysclk
# 
# Top level modules:
# 	Nios2Computer_nios2_cpu_cpu_debug_slave_sysclk
# End time: 13:45:43 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:43 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_debug_slave_tck.v -work cpu 
# -- Compiling module Nios2Computer_nios2_cpu_cpu_debug_slave_tck
# 
# Top level modules:
# 	Nios2Computer_nios2_cpu_cpu_debug_slave_tck
# End time: 13:45:43 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:43 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_debug_slave_wrapper.v -work cpu 
# -- Compiling module Nios2Computer_nios2_cpu_cpu_debug_slave_wrapper
# 
# Top level modules:
# 	Nios2Computer_nios2_cpu_cpu_debug_slave_wrapper
# End time: 13:45:43 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:43 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v -work cpu 
# -- Compiling module Nios2Computer_nios2_cpu_cpu_mult_cell
# 
# Top level modules:
# 	Nios2Computer_nios2_cpu_cpu_mult_cell
# End time: 13:45:43 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:44 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_test_bench.v -work cpu 
# -- Compiling module Nios2Computer_nios2_cpu_cpu_test_bench
# 
# Top level modules:
# 	Nios2Computer_nios2_cpu_cpu_test_bench
# End time: 13:45:44 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:44 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_reset_controller.v -work rst_controller 
# -- Compiling module altera_reset_controller
# 
# Top level modules:
# 	altera_reset_controller
# End time: 13:45:44 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:44 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_reset_synchronizer.v -work rst_controller 
# -- Compiling module altera_reset_synchronizer
# 
# Top level modules:
# 	altera_reset_synchronizer
# End time: 13:45:44 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:44 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_irq_mapper.sv -L altera_common_sv_packages -work irq_mapper 
# -- Compiling module Nios2Computer_irq_mapper
# 
# Top level modules:
# 	Nios2Computer_irq_mapper
# End time: 13:45:44 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:44 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_mm_interconnect_0.v -work mm_interconnect_0 
# -- Compiling module Nios2Computer_mm_interconnect_0
# 
# Top level modules:
# 	Nios2Computer_mm_interconnect_0
# End time: 13:45:44 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:44 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_sysid.v -work sysid 
# -- Compiling module Nios2Computer_sysid
# 
# Top level modules:
# 	Nios2Computer_sysid
# End time: 13:45:44 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:44 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_sys_clk_timer.v -work sys_clk_timer 
# -- Compiling module Nios2Computer_sys_clk_timer
# 
# Top level modules:
# 	Nios2Computer_sys_clk_timer
# End time: 13:45:44 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:44 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v -work onchip_mem 
# -- Compiling module Nios2Computer_onchip_mem
# 
# Top level modules:
# 	Nios2Computer_onchip_mem
# End time: 13:45:44 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:44 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu.v -work nios2_cpu 
# -- Compiling module Nios2Computer_nios2_cpu
# 
# Top level modules:
# 	Nios2Computer_nios2_cpu
# End time: 13:45:44 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:44 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_led_pio.v -work led_pio 
# -- Compiling module Nios2Computer_led_pio
# 
# Top level modules:
# 	Nios2Computer_led_pio
# End time: 13:45:44 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:45 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_jtag_uart.v -work jtag_uart 
# -- Compiling module Nios2Computer_jtag_uart_sim_scfifo_w
# -- Compiling module Nios2Computer_jtag_uart_scfifo_w
# -- Compiling module Nios2Computer_jtag_uart_sim_scfifo_r
# -- Compiling module Nios2Computer_jtag_uart_scfifo_r
# -- Compiling module Nios2Computer_jtag_uart
# 
# Top level modules:
# 	Nios2Computer_jtag_uart
# End time: 13:45:45 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:45 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_avalon_reset_source.sv -L altera_common_sv_packages -work Nios2Computer_inst_reset_bfm 
# -- Compiling module altera_avalon_reset_source
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_reset_source
# End time: 13:45:45 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:45 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_conduit_bfm.sv -L altera_common_sv_packages -work Nios2Computer_inst_led_pio_ext_connection_bfm 
# -- Compiling module altera_conduit_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_conduit_bfm
# End time: 13:45:45 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:45 on Feb 18,2018
# vlog -reportprogress 300 -sv D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/altera_avalon_clock_source.sv -L altera_common_sv_packages -work Nios2Computer_inst_clk_bfm 
# -- Compiling module altera_avalon_clock_source
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_clock_source
# End time: 13:45:45 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:45 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer.v -work Nios2Computer_inst 
# -- Compiling module Nios2Computer
# 
# Top level modules:
# 	Nios2Computer
# End time: 13:45:45 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:45:45 on Feb 18,2018
# vlog -reportprogress 300 D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/Nios2Computer_tb.v 
# -- Compiling module Nios2Computer_tb
# 
# Top level modules:
# 	Nios2Computer_tb
# End time: 13:45:45 on Feb 18,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# [exec] elab
# vsim -t ps -L work -L work_lib -L altera_common_sv_packages -L error_adapter_0 -L avalon_st_adapter -L rsp_mux_001 -L rsp_mux -L rsp_demux_002 -L rsp_demux -L cmd_mux_002 -L cmd_mux -L cmd_demux_001 -L cmd_demux -L nios2_cpu_data_master_limiter -L router_004 -L router_002 -L router_001 -L router -L jtag_uart_avalon_jtag_slave_agent_rsp_fifo -L jtag_uart_avalon_jtag_slave_agent -L nios2_cpu_data_master_agent -L jtag_uart_avalon_jtag_slave_translator -L nios2_cpu_data_master_translator -L cpu -L rst_controller -L irq_mapper -L mm_interconnect_0 -L sysid -L sys_clk_timer -L onchip_mem -L nios2_cpu -L led_pio -L jtag_uart -L Nios2Computer_inst_reset_bfm -L Nios2Computer_inst_led_pio_ext_connection_bfm -L Nios2Computer_inst_clk_bfm -L Nios2Computer_inst -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver Nios2Computer_tb 
# Start time: 13:45:46 on Feb 18,2018
# Loading work.Nios2Computer_tb
# Loading Nios2Computer_inst.Nios2Computer
# Loading jtag_uart.Nios2Computer_jtag_uart
# Loading jtag_uart.Nios2Computer_jtag_uart_scfifo_w
# Loading jtag_uart.Nios2Computer_jtag_uart_sim_scfifo_w
# Loading jtag_uart.Nios2Computer_jtag_uart_scfifo_r
# Loading jtag_uart.Nios2Computer_jtag_uart_sim_scfifo_r
# Loading led_pio.Nios2Computer_led_pio
# Loading nios2_cpu.Nios2Computer_nios2_cpu
# Loading cpu.Nios2Computer_nios2_cpu_cpu
# Loading altera_mf_ver.altera_std_synchronizer
# Loading altera_mf_ver.altsyncram
# Loading cpu.Nios2Computer_nios2_cpu_cpu_debug_slave_wrapper
# Loading cpu.Nios2Computer_nios2_cpu_cpu_debug_slave_tck
# Loading cpu.Nios2Computer_nios2_cpu_cpu_debug_slave_sysclk
# Loading cpu.Nios2Computer_nios2_cpu_cpu_mult_cell
# Loading sv_std.std
# Loading altera_lnsim_ver.altera_mult_add
# Loading altera_lnsim_ver.altera_mult_add_rtl
# Loading altera_lnsim_ver.ama_register_function
# Loading altera_lnsim_ver.ama_data_split_reg_ext_function
# Loading altera_lnsim_ver.ama_dynamic_signed_function
# Loading altera_lnsim_ver.ama_preadder_function
# Loading altera_lnsim_ver.ama_adder_function
# Loading altera_lnsim_ver.ama_signed_extension_function
# Loading altera_lnsim_ver.ama_multiplier_function
# Loading cpu.Nios2Computer_nios2_cpu_cpu_test_bench
# Loading sgate_ver.oper_add
# Loading lpm_ver.lpm_add_sub
# Loading sgate_ver.oper_less_than
# Loading onchip_mem.Nios2Computer_onchip_mem
# Loading sys_clk_timer.Nios2Computer_sys_clk_timer
# Loading sysid.Nios2Computer_sysid
# Loading mm_interconnect_0.Nios2Computer_mm_interconnect_0
# Loading nios2_cpu_data_master_translator.altera_merlin_master_translator
# Loading jtag_uart_avalon_jtag_slave_translator.altera_merlin_slave_translator
# Loading nios2_cpu_data_master_agent.altera_merlin_master_agent
# Loading jtag_uart_avalon_jtag_slave_agent.altera_merlin_slave_agent
# Loading jtag_uart_avalon_jtag_slave_agent.altera_merlin_burst_uncompressor
# Loading nios2_cpu_data_master_limiter.altera_avalon_sc_fifo
# Loading router.Nios2Computer_mm_interconnect_0_router
# Loading router.Nios2Computer_mm_interconnect_0_router_default_decode
# Loading router_001.Nios2Computer_mm_interconnect_0_router_001
# Loading router_001.Nios2Computer_mm_interconnect_0_router_001_default_decode
# Loading router_002.Nios2Computer_mm_interconnect_0_router_002
# Loading router_002.Nios2Computer_mm_interconnect_0_router_002_default_decode
# Loading router_004.Nios2Computer_mm_interconnect_0_router_004
# Loading router_004.Nios2Computer_mm_interconnect_0_router_004_default_decode
# Loading nios2_cpu_data_master_limiter.altera_merlin_traffic_limiter
# Loading cmd_demux.Nios2Computer_mm_interconnect_0_cmd_demux
# Loading cmd_demux_001.Nios2Computer_mm_interconnect_0_cmd_demux_001
# Loading cmd_mux.Nios2Computer_mm_interconnect_0_cmd_mux
# Loading cmd_mux_002.Nios2Computer_mm_interconnect_0_cmd_mux_002
# Loading cmd_mux_002.altera_merlin_arbitrator
# Loading cmd_mux_002.altera_merlin_arb_adder
# Loading rsp_demux.Nios2Computer_mm_interconnect_0_rsp_demux
# Loading rsp_demux_002.Nios2Computer_mm_interconnect_0_rsp_demux_002
# Loading rsp_mux.Nios2Computer_mm_interconnect_0_rsp_mux
# Loading rsp_mux.altera_merlin_arbitrator
# Loading rsp_mux.altera_merlin_arb_adder
# Loading rsp_mux_001.Nios2Computer_mm_interconnect_0_rsp_mux_001
# Loading rsp_mux_001.altera_merlin_arbitrator
# Loading rsp_mux_001.altera_merlin_arb_adder
# Loading avalon_st_adapter.Nios2Computer_mm_interconnect_0_avalon_st_adapter
# Loading error_adapter_0.Nios2Computer_mm_interconnect_0_avalon_st_adapter_error_adapter_0
# Loading irq_mapper.Nios2Computer_irq_mapper
# Loading rst_controller.altera_reset_controller
# Loading altera_common_sv_packages.verbosity_pkg
# Loading Nios2Computer_inst_clk_bfm.altera_avalon_clock_source
# Loading Nios2Computer_inst_led_pio_ext_connection_bfm.altera_conduit_bfm
# Loading Nios2Computer_inst_reset_bfm.altera_avalon_reset_source
# Loading altera_mf_ver.altsyncram_body
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION
# Loading rst_controller.altera_reset_synchronizer
# ** Warning: (vsim-8311) System Verilog assertions are supported only in Questasim.
# ** Warning: (vsim-3017) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer.v(66): [TFMPC] - Too few port connections. Expected 12, found 10.
#    Time: 0 ps  Iteration: 0  Instance: /Nios2Computer_tb/nios2computer_inst/jtag_uart File: D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_jtag_uart.v
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer.v(66): [TFMPC] - Missing connection for port 'dataavailable'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer.v(66): [TFMPC] - Missing connection for port 'readyfordata'.
# ** Warning: (vsim-3017) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Too few port connections. Expected 58, found 6.
#    Time: 0 ps  Iteration: 0  Instance: /Nios2Computer_tb/nios2computer_inst/nios2_cpu/cpu/n0il0Oi/the_altmult_add_p1 File: /build/swbuild/SJ/nightly/17.1std/590/l64/work/modelsim/eda/sim_lib/altera_lnsim.sv
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'datac'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'scanina'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'scaninb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'sourcea'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'sourceb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'clock3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'clock2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'clock1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'aclr3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'aclr2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'aclr1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'sclr3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'sclr2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'sclr1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'sclr0'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'ena3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'ena2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'ena1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'signa'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'signb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'addnsub1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'addnsub3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'scanouta'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'scanoutb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'mult01_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'mult23_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'mult01_saturation'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'mult23_saturation'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'addnsub1_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'addnsub3_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'mult0_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'mult1_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'mult2_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'mult3_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'output_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'chainout_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'output_saturate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'chainout_saturate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'overflow'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'chainout_sat_overflow'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'chainin'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'zero_chainout'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'rotate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'shift_right'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'zero_loopback'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'accum_sload'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'sload_accum'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'negate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'coefsel0'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'coefsel1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'coefsel2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(55): [TFMPC] - Missing connection for port 'coefsel3'.
# ** Warning: (vsim-3017) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Too few port connections. Expected 58, found 6.
#    Time: 0 ps  Iteration: 0  Instance: /Nios2Computer_tb/nios2computer_inst/nios2_cpu/cpu/n0il0Oi/the_altmult_add_p2 File: /build/swbuild/SJ/nightly/17.1std/590/l64/work/modelsim/eda/sim_lib/altera_lnsim.sv
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'datac'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'scanina'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'scaninb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'sourcea'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'sourceb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'clock3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'clock2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'clock1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'aclr3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'aclr2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'aclr1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'sclr3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'sclr2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'sclr1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'sclr0'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'ena3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'ena2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'ena1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'signa'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'signb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'addnsub1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'addnsub3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'scanouta'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'scanoutb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'mult01_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'mult23_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'mult01_saturation'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'mult23_saturation'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'addnsub1_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'addnsub3_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'mult0_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'mult1_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'mult2_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'mult3_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'output_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'chainout_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'output_saturate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'chainout_saturate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'overflow'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'chainout_sat_overflow'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'chainin'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'zero_chainout'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'rotate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'shift_right'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'zero_loopback'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'accum_sload'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'sload_accum'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'negate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'coefsel0'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'coefsel1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'coefsel2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(94): [TFMPC] - Missing connection for port 'coefsel3'.
# ** Warning: (vsim-3017) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Too few port connections. Expected 58, found 6.
#    Time: 0 ps  Iteration: 0  Instance: /Nios2Computer_tb/nios2computer_inst/nios2_cpu/cpu/n0il0Oi/the_altmult_add_p3 File: /build/swbuild/SJ/nightly/17.1std/590/l64/work/modelsim/eda/sim_lib/altera_lnsim.sv
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'datac'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'scanina'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'scaninb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'sourcea'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'sourceb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'clock3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'clock2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'clock1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'aclr3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'aclr2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'aclr1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'sclr3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'sclr2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'sclr1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'sclr0'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'ena3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'ena2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'ena1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'signa'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'signb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'addnsub1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'addnsub3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'scanouta'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'scanoutb'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'mult01_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'mult23_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'mult01_saturation'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'mult23_saturation'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'addnsub1_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'addnsub3_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'mult0_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'mult1_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'mult2_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'mult3_is_saturated'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'output_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'chainout_round'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'output_saturate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'chainout_saturate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'overflow'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'chainout_sat_overflow'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'chainin'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'zero_chainout'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'rotate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'shift_right'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'zero_loopback'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'accum_sload'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'sload_accum'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'negate'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'coefsel0'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'coefsel1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'coefsel2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_nios2_cpu_cpu_mult_cell.v(133): [TFMPC] - Missing connection for port 'coefsel3'.
# ** Warning: (vsim-3017) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Too few port connections. Expected 23, found 7.
#    Time: 0 ps  Iteration: 0  Instance: /Nios2Computer_tb/nios2computer_inst/onchip_mem/the_altsyncram File: /build/swbuild/SJ/nightly/17.1std/590/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'wren_b'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'rden_a'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'rden_b'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'data_b'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'address_b'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'clock1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'clocken1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'clocken2'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'clocken3'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'aclr0'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'aclr1'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'byteena_b'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'addressstall_a'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'addressstall_b'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'q_b'.
# ** Warning: (vsim-3722) D:/OneDrive/UVA/TeachingInternship/Nios2Computer/Nios2Computer/testbench/Nios2Computer_tb/simulation/submodules/Nios2Computer_onchip_mem.v(60): [TFMPC] - Missing connection for port 'eccstatus'.
# ** Warning: Design size of 20468 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
# Expect performance to be adversely affected.
#  
add wave -position insertpoint  \
sim:/Nios2Computer_tb/nios2computer_inst_clk_bfm_clk_clk \
sim:/Nios2Computer_tb/nios2computer_inst_led_pio_ext_connection_export \
sim:/Nios2Computer_tb/nios2computer_inst_reset_bfm_reset_reset
add wave -position insertpoint sim:/Nios2Computer_tb/nios2computer_inst/led_pio/*
add wave -position insertpoint sim:/Nios2Computer_tb/nios2computer_inst/nios2_cpu/*
add wave -position insertpoint sim:/Nios2Computer_tb/nios2computer_inst/onchip_mem/*
run
# Warning: DONT_CARE value for read_during_write_mode_port_a is not supported in Stratix device family, it might cause incorrect behavioural simulation result
# Time: 0  Instance: Nios2Computer_tb.nios2computer_inst.onchip_mem.the_altsyncram.m_default.altsyncram_inst
#                    0: INFO: Nios2Computer_tb.nios2computer_inst_clk_bfm.__hello: - Hello from altera_clock_source.
#                    0: INFO: Nios2Computer_tb.nios2computer_inst_clk_bfm.__hello: -   $Revision: #1 $
#                    0: INFO: Nios2Computer_tb.nios2computer_inst_clk_bfm.__hello: -   $Date: 2017/07/30 $
#                    0: INFO: Nios2Computer_tb.nios2computer_inst_clk_bfm.__hello: -   CLOCK_RATE = 50000000 Hz
#                    0: INFO: ------------------------------------------------------------
#                    0: INFO: Nios2Computer_tb.nios2computer_inst_reset_bfm.__hello: - Hello from altera_reset_source
#                    0: INFO: Nios2Computer_tb.nios2computer_inst_reset_bfm.__hello: -   $Revision: #1 $
#                    0: INFO: Nios2Computer_tb.nios2computer_inst_reset_bfm.__hello: -   $Date: 2017/07/30 $
#                    0: INFO: Nios2Computer_tb.nios2computer_inst_reset_bfm.__hello: -   ASSERT_HIGH_RESET = 0
#                    0: INFO: Nios2Computer_tb.nios2computer_inst_reset_bfm.__hello: -   INITIAL_RESET_CYCLES = 50
#                    0: INFO: ------------------------------------------------------------
#                    0: INFO: Nios2Computer_tb.nios2computer_inst_reset_bfm.reset_assert: Reset asserted
run
run
run
run
run 500ms
#               990000: INFO: Nios2Computer_tb.nios2computer_inst_reset_bfm.reset_deassert: Reset deasserted
# 
# 
# **************************
# * Hello from Nios II!    *
# * Counting from 00 to ff *
# **************************
# End time: 14:25:54 on Feb 18,2018, Elapsed time: 0:40:08
# Errors: 0, Warnings: 181
